Side-channel attacks pose a severe threat to both software and hardware cryptographic implementations. Current literature presents various countermeasures against these kinds of attacks, based on approaches such as hiding or masking, implemented either in software, or on register–transfer level or gate level in hardware. However, emerging trends in hardware design lean towards a system-level approach, allowing for faster, less error-prone, design process, an efficient hardware/software co-design, or sophisticated validation, verification, and (co)simulation strategies. In this paper, we propose a Boolean masking scheme suitable for high-level synthesis of substitution–permutation network-based encryption. We implement both unprotected and protected PRESENT, AES/Rijndael and Serpent encryption in C language, utilizing the concept of dynamic logic reconfiguration, synthesize it for Xilinx FPGA, and we compare our results regarding time and area utilization. We evaluate the effectiveness of proposed countermeasures using both specific and non-specific t-test leakage assessment methodology. We discuss the leakage assessment results, and we identify and discuss the related limitations of the system-level approach and the high-level synthesis.

旁道攻击对软件和硬件加密实现都构成了严重威胁。当前的文献针对这些类型的攻击提出了各种对策，基于隐藏或屏蔽等方法，在软件中实现，或者在硬件中的寄存器传输级别或门级别实现。然而，硬件设计的新兴趋势倾向于系统级方法，允许更快、更不容易出错的设计过程、高效的硬件/软件协同设计或复杂的验证、验证和（协同）仿真策略。在本文中，我们提出了一种布尔掩码方案，适用于基于替换-置换网络的加密的高级综合。我们在 C 语言中实现了不受保护和受保护的 PRESENT、AES/Rijndael 和 Serpent 加密，利用动态逻辑重配置的概念，将其综合用于 Xilinx FPGA，并比较我们在时间和面积利用率方面的结果。我们使用特定和非特定 t 检验泄漏评估方法来评估所提议对策的有效性。我们讨论泄漏评估结果，并确定和讨论系统级方法和高级综合的相关局限性。