Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image. The architecture data path consists of eight and six stages of pipeline capable of watermarking on the pixel-based operation and vector-based operation, respectively. The dual image watermarking architecture data path consists of a 13-stage pipeline. Pipeline and parallelism mechanisms are used to improve throughput. To improve the performance in discrete cosine transform operations at the frequency domain, the shift-add technique replaces the conventional multipliers. The clock gating technique is employed to reduce the power by preventing unnecessary switching in a path. Hardware implementation of the algorithm is tested in Intel Cyclone FPGA with the device of EP4CGX22CF19C6, with which the throughput achieved is 1.27Gbits/s with a total area utilization of 35digital signal processing (DSP) blocks, 378 look-up tables (LUTs) and 486 registers.

中文翻译：

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设计用于空间和频域中可见数字图像水印的混合 FPGA 架构

提出了混合现场可编程门阵列（FPGA）实现以提高可见图像水印系统的性能。可见水印处理被实现为空间域下的逐像素操作或频域中的矢量操作。所提出的方法主要用于对从各种尺寸的数码相机拍摄的图像进行水印处理。填充技术用于水印图像和原始宿主图像的大小不等。该架构数据路径由八级和六级流水线组成，分别能够对基于像素的操作和基于矢量的操作进行水印处理。双图像水印架构数据路径由 13 级流水线组成。管道和并行机制用于提高吞吐量。为了提高频域离散余弦变换运算的性能，移位相加技术取代了传统的乘法器。时钟门控技术用于通过防止路径中不必要的切换来降低功耗。该算法的硬件实现在 Intel Cyclone FPGA 中使用 EP4CGX22CF19C6 器件进行了测试，实现的吞吐量为 1.27Gbits/s，总面积利用率为 35数字信号处理 (DSP) 模块、378 个查找表 (LUT) 和 486 个寄存器。