Spin-torque-based magnetic random access memories (MRAMs) have emerged as a promising option for next-generation data-centric computing systems. Multi-level cell (MLC) configuration is an efficient method to increase storage density. In this article, we propose a series triple-level cell (sTLC) architecture based on spin-transfer torque (STT) and spin-orbit torque (SOT) switching mechanisms. The proposed hybrid STT/SOT sTLC MRAM architecture is capable of storing 3 bits of data using a maximum of two writing steps. However, most of the switching transitions (72%) use only single-step writing. The simulation results of the sTLC MRAM showed 82% and 68% saving in the write energy compared with previously published STT and STT-/SOT-based TLC structures, respectively. One-step parallel read operation for sTLC is presented in this work that enables ultra-fast reading of 3 bits of data. Furthermore, a novel sTLC-based computing-in memory (CiM) architecture is proposed, and high-performance AND/OR/XOR and magnetic full-adder (MFA) logic circuits have been implemented. The proposed sTLC-based CiM MFA shows 33% lesser transistor counts with nearly equivalent energy performance in comparison to the recently published spin-Hall effect (SHE)-based CiM MFA.

中文翻译：

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使用基于 STT/SOT 的系列三级单元 MRAM 的高性能内存计算架构


基于自旋扭矩的磁性随机存取存储器 (MRAM) 已成为下一代以数据为中心的计算系统的一个有前景的选择。多层单元（MLC）配置是提高存储密度的有效方法。在本文中，我们提出了一种基于自旋转移矩（STT）和自旋轨道矩（SOT）切换机制的串联三能级单元（sTLC）架构。所提出的混合 STT/SOT sTLC MRAM 架构能够使用最多两个写入步骤存储 3 位数据。然而，大多数切换转换（72%）仅使用单步写入。 sTLC MRAM 的仿真结果显示，与之前发布的 STT 和基于 STT/SOT 的 TLC 结构相比，写入能量分别节省了 82% 和 68%。这项工作提出了 sTLC 的一步并行读取操作，可实现 3 位数据的超快速读取。此外，提出了一种新颖的基于sTLC的内存计算（CiM）架构，并实现了高性能AND/OR/XOR和磁全加器（MFA）逻辑电路。与最近发布的基于自旋霍尔效应 (SHE) 的 CiM MFA 相比，所提出的基于 sTLC 的 CiM MFA 的晶体管数量减少了 33%，而能量性能几乎相同。