Due to the increasing throughput of high-performance integrated circuits, the power consumption of recent high-performance computing systems has grown significantly, leading to greater on-chip current demand. The large current flowing within the power delivery system produces challenging issues, such as electromigration, low power efficiency, and thermal hot spots. To reduce on-chip current demand, voltage stacking has become a topic of growing interest within the industrial and academic communities. The challenges of power delivery for on-chip voltage stacked systems are, however, significant. The power delivery system connects individual stacks and stacks to converters. Challenges include cross-core current paths. A tile-based power delivery design methodology is proposed for high current, voltage stacked systems. The tile-based power delivery system provides net separation, low parasitic impedance, and a scalable design process. The tile shape eases the design and characterization of the parasitic impedance, making this methodology effective for early stage exploration of the power delivery system within voltage stacked structures.

中文翻译：

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用于高电流、电压堆叠系统的基于区块的供电网络

由于高性能集成电路的吞吐量不断增加，最近的高性能计算系统的功耗显着增加，导致更大的片上电流需求。电力输送系统内流动的大电流会产生具有挑战性的问题，例如电迁移、低功率效率和热点。为了减少片上电流需求，电压堆叠已成为工业界和学术界越来越感兴趣的话题。然而，片上电压堆叠系统的供电挑战是巨大的。电力输送系统将单个堆栈和堆栈连接到转换器。挑战包括跨核电流路径。针对高电流、电压堆叠系统提出了一种基于区块的电力传输设计方法。基于瓦片的电力传输系统提供净分离、低寄生阻抗和可扩展的设计过程。瓦片形状简化了寄生阻抗的设计和表征，使这种方法对于电压堆叠结构内的电力输送系统的早期探索有效。