Encryption schemes like AES require finite field modular multiplication. The encryption speed is highly dependent on the performance of the finite field multiplier. Several high-speed systolic bit parallel multipliers with low area complexity have been proposed in the literature. In this paper, a modular multiplication algorithm is used to propose a bit parallel polynomial basis systolic multiplier which has achieved 89% less and 17% less area-delay product than the best existing multipliers. It has been observed that the area complexity of the proposed systolic multiplier for irreducible polynomials matches with the best-reported multiplier with 17% less time complexity. The results are further verified with the help of the FPGA implementation of the proposed multiplier for m = 8,163. Being generic, the proposed multiplier can be optimized further for trinomials and pentanomials.

像 AES 这样的加密方案需要有限域模乘法。加密速度高度依赖于有限域乘法器的性能。文献中已经提出了几种具有低面积复杂度的高速脉动位并行乘法器。在本文中，使用模乘算法提出了一种位并行多项式基收缩乘法器，该乘法器比现有的最佳乘法器减少了 89% 和 17% 的面积延迟积。已经观察到，所提出的不可约多项式的收缩乘法器的面积复杂度与最佳报告的乘法器相匹配，时间复杂度降低了 17%。在 m = 8,163 的提议乘法器的 FPGA 实现的帮助下，进一步验证了结果。泛泛而谈，