We fabricated vertical-channel charge-trap memory thin film transistors (V-CTM TFTs) using an In–Ga–Zn–O channel and ZnO charge trap layers, in which a solution-processed SiO₂ spacer pattern was introduced to scale down the vertical-channel length below 190 nm. The vertical gate-stack structure was implemented by atomic-layer deposition with excellent film conformality. The V-CTM TFTs with channel lengths of 190 (S1) and 140 nm (S2) showed charge-trap-assisted wide memory windows of 12.0 and 10.1 V, respectively. The memory margins between the on- and off-programmed currents were estimated to be 1.2 × 10⁵ and 5.1 × 10² with a program pulse duration of 100 ms for S1 and S2, respectively. The programmed states did not exhibit any degradation with a lapse of retention for 10⁴ s. With reducing the channel length, the number of endurance cycles decreased from 5000 to 3000 cycles. A vertical integration of oxide-based CTM device scaled down to sub-150 nm could be verified to show sound nonvolatile memory operations, even though there remain some technical issues such as a higher level of off-current for S2.

中文翻译：

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使用氧化物半导体有源层和陷阱层表征纳米级垂直沟道电荷陷阱存储器薄膜晶体管

我们使用 In-Ga-Zn-O 通道和 ZnO 电荷陷阱层制造了垂直通道电荷陷阱存储薄膜晶体管 (V-CTM TFT)，其中引入了溶液处理的 SiO ₂间隔图案以按比例缩小垂直通道长度低于 190 nm。垂直栅堆叠结构是通过原子层沉积实现的，具有出色的薄膜保形性。沟道长度为 190 (S1) 和 140 nm (S2) 的 V-CTM TFT 分别显示出 12.0 和 10.1 V 的电荷陷阱辅助宽存储窗口。接通和断开编程电流之间的存储器裕量估计为 1.2 × 10 ⁵和 5.1 × 10 ²S1 和 S2 的编程脉冲持续时间分别为 100 ms。编程状态在保留 10 ⁴ 秒后没有表现出任何退化。随着通道长度的减少，耐久循环次数从 5000 次减少到 3000 次。尽管仍存在一些技术问题，例如 S2 的关断电流水平较高，但可以验证缩小到 150 nm 以下的基于氧化物的 CTM 器件的垂直集成，以显示良好的非易失性存储器操作。