The bit parallel multiplication scheme is characterized by an important feature called concurrency, which makes its execution faster. The output through this scheme is generated in every clock cycle, after taking ‘m’ clock cycles in the beginning. In this paper, a polynomial basis systolic multiplier over irreducible polynomials ($x^m+t_{m-1}{x}^{m-1}+..\mathrm{..}{t}_2{x}^2+t_1{x}^1+t_0$) in GF(2^m) is designed specifically for odd ‘m’, which takes ‘m’ clock cycles and this is further, used to design the low complexity bit-parallel architecture for general irreducible polynomials and trinomials ($x^m+x^k+1$). The area complexity of the proposed multiplier for general irreducible polynomials matches with the best existing multiplier with a 17% reduction in time complexity due to a considerable decrease in critical path delay. To the best of our knowledge, the area-delay product of the proposed multipliers is the lowest achieved when compared with the best multipliers available in the literature. FPGA implementation results also show that the proposed multiplier has 59% less space complexity and 47% less time complexity than the best-reported multiplier for m = 233.

位并行乘法方案的特点是一个称为并发的重要特性，这使得它的执行速度更快。在开始时经过“m”个时钟周期后，每个时钟周期都会生成通过该方案的输出。在本文中，在不可约多项式上的多项式基收缩乘子 ($X^{米}+{吨}_{米-1}{X}^{米-1}+..\mathrm{..}{吨}_2{X}^2+{吨}_1{X}^1+{吨}_0$) 在 GF(2 ^m ) 中是专门为奇数“m”设计的，它需要“m”个时钟周期，这进一步用于设计一般不可约多项式和三项式的低复杂度位并行架构（$X^{米}+X^{克}+1$）。由于关键路径延迟的显着减少，所提出的用于一般不可约多项式的乘法器的面积复杂度与现有的最佳乘法器相匹配，时间复杂度降低了 17%。据我们所知，与文献中可用的最佳乘法器相比，所提出的乘法器的面积延迟积是最低的。FPGA 实现结果还表明，与 m = 233 时最佳报告的乘法器相比，所提出的乘法器的空间复杂度降低了 59%，时间复杂度降低了 47%。