Structural mechanics and mechanical reliability issues are becoming more and more challenging in the semiconductor industry due to the continuous trend of the device dimensional shrinkage and simultaneous increased operative temperature and power density. As main consequence of the downsizing and more aggressive operative conditions, the mechanical robustness assessment is now having a central role in the device engineering and assessment phase. The risk of mechanical crack in the brittle oxide layers, which are embedded in pad stacks, increases during the device manufacturing processes such as the electrical wafer testing and during wire bonding. This risk increases with the presence of intrinsic mechanical stress in individual layers resulting from the metal grain growth mechanisms, the stack layers’ interfacial mismatches in coefficients of thermal expansion and the temperature stress induced by doping diffusion and film deposition. The current trend of innovation in the electronic industry is going over the semiconductor material itself and it is now impacting the improvement of the Back-End of Line. Key actors are becoming the interactions between the semiconductor die and the device packaging such as adhesion layers, barriers and metal stacks. In the present work, different pad structures have been structurally analyzed and benchmarked. The experimental characterization of the pad structures has been done through a flat punch nano-indentation to investigate on the mechanical strength and the crack propagation. The considered mechanical load reproduces the vertical impact force applied during wire bonding process to create the bond-pad electrical interconnection. The obtained testing results have been compared to finite element models to analyze the stress distribution through the different layers’ stacks. Scope of this work is to demonstrate the validity of the proposed integrated numerical/experimental methodology, showing the impact of the metal connections layouts by the analysis of the stress notch factors and crack propagation behaviour.

由于器件尺寸缩小的持续趋势以及同时增加的工作温度和功率密度，结构力学和机械可靠性问题在半导体行业中变得越来越具有挑战性。作为缩小尺寸和更具侵略性的操作条件的主要结果，机械稳健性评估现在在设备工程和评估阶段发挥着核心作用。在器件制造过程（例如电子晶圆测试和引线键合）中，嵌入焊盘堆叠中的脆性氧化层出现机械裂纹的风险会增加。这种风险随着金属晶粒生长机制在各个层中存在固有机械应力而增加，堆叠层的界面在热膨胀系数和由掺杂扩散和薄膜沉积引起的温度应力方面不匹配。当前电子行业的创新趋势正在超越半导体材料本身，它现在正在影响生产线后端的改进。关键参与者正在成为半导体芯片和设备封装之间的相互作用，例如粘合层、屏障和金属堆叠。在目前的工作中，不同的焊盘结构已经进行了结构分析和基准测试。焊盘结构的实验表征是通过平面冲压纳米压痕完成的，以研究机械强度和裂纹扩展。所考虑的机械负载再现了引线键合过程中施加的垂直冲击力，以创建键合焊盘电气互连。将获得的测试结果与有限元模型进行比较，以分析通过不同层堆叠的应力分布。这项工作的范围是证明所提出的综合数值/实验方法的有效性，通过分析应力缺口因素和裂纹扩展行为来显示金属连接布局的影响。