Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopper-stabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036mm2{0.036}\,{{\rm {mm}}^2}, an input referred noise of 1.32μVrms{1.32}\,\mu {\rm {V}}_{\text{rms}} (1 to 200 Hz) and 3.36μVrms{3.36}\,\mu {\rm {V}}_{\text{rms}} (0.2 to 10 kHz), power consumption of 13.7μW{13.7}\,{\mu {\rm W}} from 1.8 V supply, as well as CMRR and PSRR ≥\ge 83 dB at 50 Hz.

中文翻译：

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具有输入阻抗提升和抑制偏移引起的电荷转移的斩波神经前端


现代神经调节系统通常提供大量记录和刺激通道，这减少了每个通道的可用功率和面积预算。为了在面积限制日益严格的情况下保持必要的输入参考噪声性能，斩波神经前端通常是选择的方式，因为斩波稳定可以同时改善 (1/f) 噪声和面积消耗。现有技术中已经通过基于输入处的电压缓冲器的阻抗增强器解决了由此产生的输入阻抗急剧减小的问题。这些缓冲器对大输入电容器进行预充电，减少从电极吸取的电荷，并有效地提高输入阻抗。这些缓冲器上的偏移直接转化为电极的电荷转移，这会加速电极老化。为了解决这个问题，提出了一种具有超低时间平均偏移的电压缓冲器，它通过周期性重新配置来消除偏移，从而最大限度地减少意外的电荷转移。本文详细解释了背景和电路设计，并介绍了采用 180 nm HV CMOS 工艺实现的原型的测量结果。测量结果证实，发生了与信号无关的缓冲器偏移引起的电荷转移，并且可以通过所提出的缓冲器重新配置来减轻电荷转移，而不会对输入阻抗升压器的操作产生不利影响。所提出的神经记录器前端实现了最先进的性能，面积消耗为 0.036mm2{0.036}\,{{\rm {mm}}^2}，输入参考噪声为 1.32μVrms{1.32}\,\ mu {\rm {V}}_{\text{rms}}（1 至 200 Hz）和 3.36μVrms{3.36}\,\mu {\rm {V}}_{\text{rms}}（0.2 至10 kHz），功耗为 13.7μW{13.7}\,{\mu {\rm W}} 从 1 开始。8 V 电源，50 Hz 时 CMRR 和 PSRR ≥ 83 dB。