In this paper, two efficient low-cost and high-throughput structures of the SPONGENT lightweight hash function are presented. Two structures are called full data-path width (parallel) and 4-bit serialized. The serialized architecture is designed by using one multi-task shift register in the round computations with minimum hardware resources. The area consumed in this structure is lower than that of the full data-path structure but the number of clock cycles is increased. The speed computation of the full data-path is higher compared to the 4-bit serialized structure of the SPONGENT hash function because the data are computed in a parallel form. To improving the timing characteristics, we implement the S-box block as the complex block in the SPONGENT hash function based on an Area$\times$Delay optimized circuit. A large number of gates, in the structure, have been implemented by 2-input NAND and 2-input NOR gates in order to reduce delay and area. The performance measurement of the proposed structures is performed by evaluating the parameters such as area consumption, computation time, critical path delay (CPD), throughput, and throughput/area. The implementation results are achieved for all variants of the SPONGENT hash function in 180 nm CMOS technology. The results of area consumption (for 4-bit serialized structure) and throughput (for full data-path structure) show improvements compared to previous works. For area-constrained applications, the proposed structure with a lower data-path width is an appropriate choice. The full data-path width structure can be used for the high-speed and high-throughout cryptographic applications.

在本文中，提出了 SPONGENT 轻量级哈希函数的两种高效低成本和高吞吐量结构。两种结构称为全数据路径宽度（并行）和 4 位序列化。串行化架构是通过在一轮计算中使用一个多任务移位寄存器以最少的硬件资源设计的。这种结构所消耗的面积比全数据路径结构要小，但时钟周期数增加了。与 SPONGENT 哈希函数的 4 位序列化结构相比，完整数据路径的计算速度更高，因为数据是以并行形式计算的。为了改善时序特性，我们将 S-box 块实现为基于区域的 SPONGENT 哈希函数中的复杂块$\times$延迟优化电路。结构中的大量门已由2输入NAND和2输入NOR门实现，以减少延迟和面积。所提出结构的性能测量是通过评估诸如面积消耗、计算时间、关键路径延迟 (CPD)、吞吐量和吞吐量/面积等参数来执行的。在 180 nm CMOS 技术中，SPONGENT 哈希函数的所有变体都获得了实现结果。与之前的工作相比，面积消耗（对于 4 位序列化结构）和吞吐量（对于完整数据路径结构）的结果显示出改进。对于区域受限的应用，建议的具有较低数据路径宽度的结构是合适的选择。