This letter reports a novel approach for ultra-low stress die attachment for microelectromechanical system (MEMS) devices based on a stacked multilayer substrate. The substrate consists of stacked layers of alternating low and high coefficient of thermal expansion (CTE) materials. The effective CTE of the substrate is determined by adjusting the thickness ratio of the stacked layers, hence, the CTE mismatch between the substrate and the MEMS devices can be tuned to minimize the packaging stress during die attachment. Simplified block structures are fabricated to verify the effectiveness of the reported approach. The measurement results agree well with the theoretical analysis, and the finite-element method (FEM) simulation. The maximum deflection of a packaged $3\times 5$ mm ² die is reduced to be lower than 10 nm using a quartz glass-alumina stacked layer substrate, which is approximately 30 times lower than that using a conventional alumina substrate. Moreover, the thermal behavior of the packaging chips utilizing this approach is measured in a temperature range of 25 °C to 150 °C. This work highlights an effective and simple way for the chip-scale package of MEMS devices with strict requirements for low packaging stress. [2021-0043]

中文翻译：

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基于堆叠多层基板的超低应力芯片连接

这封信报告了一种用于基于堆叠多层基板的微机电系统 (MEMS) 设备的超低应力芯片连接的新方法。基板由交替的低和高热膨胀系数 (CTE) 材料的堆叠层组成。基板的有效 CTE 是通过调整堆叠层的厚度比来确定的，因此，可以调整基板和 MEMS 器件之间的 CTE 失配，以最大限度地减少芯片附着过程中的封装应力。制造简化的块结构以验证所报告方法的有效性。测量结果与理论分析和有限元法（FEM）模拟非常吻合。包装件的最大挠度 $3\乘以5$ 使用石英玻璃-氧化铝叠层基板将mm ²裸片减小到低于10nm，这比使用传统氧化铝基板的尺寸小 约30倍。此外，使用这种方法的封装芯片的热行为是在 25°C 到 150°C 的温度范围内测量的。这项工作为对低封装应力有严格要求的 MEMS 器件的芯片级封装提供了一种有效且简单的方法。[2021-0043]