Single-slope analog-to-digital converter (SS ADC) and time-to-digital converter (TDC) architectures in their high-speed or high-resolution status tend to either have high-power consumption or occupy large area. However, using the hybrid structure of these two, although synchronizing them might be a limiting factor, can solve the area and power consumption issues. In this paper, a 4-bit SS ADC is combined with a 4-bit TDC. Moreover, a new low-powered continuous-time comparator architecture is designed to adjust its current based on not only the inputs amplitude but also their proximity near the flip point. In addition, a novel delay correction technique is utilized to resolve its nonlinear propagation delay. The presented technique reduces 90% nonlinearity of the comparator’s propagation delay and decreases its delay variation to 450ps. Using TSMC CMOS 130nm technology with a sampling frequency of 5.88MHz, the simulation result illustrates 788μW power consumption with the master clock frequency of 100MHz while an integral nonlinearity (INL) of −1.41–+0.76LSB and a differential nonlinearity (DNL) of −1.05–+0.05LSB is achieved in 625ps resolution. Finally, figure-of-merit (FoM) depicts 31.2fJ/conv. step. The presented converter can be used in CMOS image sensors and multi-resolution applications.

中文翻译：

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具有改进的连续时间比较器的 8 位混合 TDC/单斜率 ADC

单斜率模数转换器 (SS ADC) 和时间数字转换器 (TDC) 架构在其高速或高分辨率状态下往往具有高功耗或占用大面积。然而，使用这两者的混合结构，虽然同步它们可能是一个限制因素，但可以解决面积和功耗问题。在本文中，4 位 SS ADC 与 4 位 TDC 相结合。此外，一种新的低功耗连续时间比较器架构旨在调整其电流，不仅基于输入幅度，还基于它们在翻转点附近的接近度。此外，利用一种新颖的延迟校正技术来解决其非线性传播延迟。所提出的技术降低了比较器传播延迟的 90% 非线性并将其延迟变化降低到 450附言。使用台积电 CMOS 130nm 技术，采样频率为 5.88MHz，仿真结果说明 788μ主时钟频率为 100 的 W 功耗MHz，而积分非线性（INL）为-1.41–+0.76LSB 和微分非线性 (DNL)-1.05–+0.05LSB 达到 625ps分辨率。最后，品质因数 (FoM) 描绘了 31.2fJ/转化率 步。所提出的转换器可用于 CMOS 图像传感器和多分辨率应用。