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Influence of Interface trap distributions over the device characteristics of AlGaN/GaN/AlInN MOS-HEMT using Cubic Spline Interpolation technique
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields ( IF 1.6 ) Pub Date : 2021-07-13 , DOI: 10.1002/jnm.2936
Sandeep Viswanathan 1 , Charles Pravin 1 , Ramesh Babu Arasamudi 2 , Prajoon Pavithran 3
Affiliation  

Traps present at the interface of oxide and barrier layers influence the device's DC and RF parameters. An investigation is carried out on the distribution of interface traps present in the AlGaN/GaN/AlInN Metal Oxide Semiconductor-High Electron Mobility Transistor (MOS-HEMT) structures. By incorporating Hafnium Oxide (HfO2) as a dielectric layer, the DC and RF parameters like current drive and Power-Added Efficiency (PAE) for the device are evaluated. The Capacitance-Voltage (CV) curves showed a shift in its values upon increase in trap density, which attributes to the position of fermi level once the threshold voltage is reached. A theoretical estimation of interface trap densities revealed distributions in the magnitude of 9.52 × 1012 cm−2 eV−1 near the mid-gap and around 3.4 × 1013 cm−2 eV−1 at the Conduction Band (CB) edge. Carrier concentration at the Two-Dimensional Electron Gas (2DEG) influences the distribution of traps at the interface, which in turn affects the on-resistance of the device. Cubic Spline Interpolation (CSI) technique is employed here to model the device parameters precisely. The higk-K dielectric material causes a high cut-off of 201 GHz for the MOS-HEMT. There is about 42% improvement in the PAE compared to the conventional MOS-HEMT device. The comparably low trap density values (1012 cm−2 eV−1) than the conventional ones, prove the high quality gate passivation features of the HfO2/AlGaN interface and could serve as a potential candidate for high power and microwave applications.

中文翻译:

界面陷阱分布对使用三次样条插值技术的 AlGaN/GaN/AlInN MOS-HEMT 器件特性的影响

氧化物和阻挡层界面处存在的陷阱会影响器件的 DC 和 RF 参数。对存在于 AlGaN/GaN/AlInN 金属氧化物半导体-高电子迁移率晶体管 (MOS-HEMT) 结构中的界面陷阱的分布进行了研究。通过将氧化铪 (HfO 2 ) 作为介电层,可以评估 DC 和 RF 参数,例如该器件的电流驱动和功率附加效率 (PAE)。电容-电压 ( CV ) 曲线显示其值随陷阱密度增加而发生变化,这归因于达到阈值电压后费米能级的位置。界面陷阱密度的理论估计揭示了 9.52 × 10 12大小的分布 cm -2  eV -1靠近中间间隙和大约 3.4 × 10 13  cm -2  eV -1在传导带 (CB) 边缘。二维电子气 (2DEG) 处的载流子浓度会影响界面处陷阱的分布,进而影响器件的导通电阻。这里采用三次样条插值 (CSI) 技术来精确建模设备参数。所述higk-K介电材料引起的MOS-HEMT的高截止201千兆赫。与传统的 MOS-HEMT 器件相比,PAE 有大约 42% 的改进。相对较低的陷阱密度值 (10 12  cm -2  eV -1) 与传统的相比,证明了 HfO 2 /AlGaN 界面的高质量栅极钝化特性,可作为高功率和微波应用的潜在候选者。
更新日期:2021-07-13
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