The growing use of Field Programmable Gate Array (FPGA) to increase application performance requires tools that simplify the digital circuit development process. Traditional approaches of Hardware Description Languages (HDLs) are complex and require specialized knowledge at a low-level abstraction. In turn, different approaches called High-Level Synthesis (HLS) aim at facilitating the development of FPGA applications, making this development process closer to those of software using programming languages such as C or C++. However, these alternatives do not properly exploit the parallelism capability of FPGAs as they are based on usual sequential approaches and, moreover, continue to depend on developer technical knowledge about the target hardware. The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative entities. This type of inference allows presenting an innovative way of implicitly achieving decoupled and decentralized solutions, thereby enabling parallelism and distribution in a level of granularity as fine as possible in the envisaged computational platform. In this context, researches on NOP have proposed the design of digital circuits based on the NOP model, called NOP Digital Hardware (DH). In this paper, it is proposed to evaluate the use of the NOP-DH to develop the well-known Bitonic Sort, which is a sort algorithm useful as benchmark. This algorithm has particular properties that are advantageous for parallel execution, especially in FPGAs. Experiments were performed to compare the performance, amount of logic elements, and maximum frequency of NOP-DH against the traditional VHDL approach. These experiments demonstrated that even with a higher abstraction level of development, NOP-DH circuits achieve similar results when compared to the traditional development in VHDL.

越来越多地使用现场可编程门阵列 (FPGA) 来提高应用程序性能，需要能够简化数字电路开发过程的工具。硬件描述语言 (HDL) 的传统方法很复杂，需要低级抽象的专业知识。反过来，称为高级综合 (HLS) 的不同方法旨在促进 FPGA 应用程序的开发，使该开发过程更接近使用 C 或C等编程语言的软件的开发过程++。然而，这些替代方案没有正确利用 FPGA 的并行能力，因为它们基于通常的顺序方法，而且，继续依赖于开发人员关于目标硬件的技术知识。面向通知的范式 (NOP) 作为开发和执行应用程序的替代方案出现。NOP 带来了基于精确通知协作实体的新推理概念。这种类型的推理允许提出一种隐式实现解耦和分散解决方案的创新方式，从而在设想的计算平台中以尽可能精细的粒度级别实现并行性和分布。在此背景下，NOP 的研究提出了基于 NOP 模型的数字电路设计，称为 NOP 数字硬件（DH）。在本文中，建议评估 NOP-DH 的使用，以开发著名的双音排序，这是一种用作基准的排序算法。该算法具有有利于并行执行的特殊属性，尤其是在 FPGA 中。进行了实验以比较 NOP-DH 与传统 VHDL 方法的性能、逻辑元件数量和最大频率。这些实验表明，即使具有更高的抽象级别的开发，与传统的 VHDL 开发相比，NOP-DH 电路也能实现类似的结果。逻辑元素的数量，以及与传统 VHDL 方法相比的 NOP-DH 的最大频率。这些实验表明，即使具有更高的抽象级别的开发，与传统的 VHDL 开发相比，NOP-DH 电路也能实现类似的结果。逻辑元素的数量，以及与传统 VHDL 方法相比的 NOP-DH 的最大频率。这些实验表明，即使具有更高的抽象级别的开发，与传统的 VHDL 开发相比，NOP-DH 电路也能实现类似的结果。