This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental ΔΣ ( IΔΣ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and IΔΣ ADCs can both achieve (very) low fixed-pattern noise values.

中文翻译：

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3D 堆叠 CMOS 图像传感器的读出架构和模数转换器的分析和比较


本文概述了 3D 堆叠 CMOS 图像传感器 (CIS) 的读出架构和模数转换器 (ADC) 及其优点和挑战。根据应用需求，将提出合适的 3D 堆叠读出架构。虽然迄今为止大多数 ADC 都是在平面 CIS 中报道的，但本文将这些设计移植到 3D 堆叠 CIS 中，并在噪声、速度和功率效率方面比较了此 3D 堆叠环境中的不同 ADC 拓扑。比较表明，与 SAR 和循环 ADC 相比，斜坡和增量 ΔΣ (IΔΣ) ADC 可以实现更好的整体性能，对于 3D 堆叠 CIS 而言，性能提高约 3 倍。此外，斜坡和 IΔΣ ADC 都可以实现（非常）低的固定模式噪声值。