Power consumption is an important limitation in designing analog-to-digital converters (ADCs) used in low-power sensing applications. This paper estimates analytically the power bound of a two-step multi-stage noise-shaping successive-approximation-register incremental ADC (two-step MASH NS-SAR IADC) proposed in our previous work. Our model considers the impacts of thermal noise, mismatch, and CMOS process (minimum feature size in CMOS technologies) on the power bounds of the proposed IADC. The analytic results show that thermal noise and CMOS process requirements determine the power consumption lower bounds in high and low resolutions, respectively. A comparison with the most competitive single-loop delta-sigma ( $\Delta \Sigma $ ) IADC shows a 3-dB higher theoretical figure-of-merit (FoM) for our proposed IADC when the resolutions are higher than 12-bit. Our proposed systematic analysis can be used to estimate the power bounds of amplifier-based NS-SAR ADCs used in either $\Delta \Sigma $ or incremental mode with multi-stage and multi-step topologies designed in various CMOS technologies. The reported analytic results are confirmed by experimental results of previously reported implementations.

中文翻译：

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基于噪声整形 SAR ADC 的两步 MASH 增量式 ADC 的功率界限分析

功耗是设计用于低功耗传感应用的模数转换器 (ADC) 的一个重要限制。本文分析估计了我们之前工作中提出的两步多级噪声整形逐次逼近寄存器增量 ADC（两步 MASH NS-SAR IADC）的功率界限。我们的模型考虑了热噪声、失配和 CMOS 工艺（CMOS 技术中的最小特征尺寸）对提议的 IADC 功率范围的影响。分析结果表明，热噪声和 CMOS 工艺要求分别决定了高分辨率和低分辨率下的功耗下限。与最具竞争力的单回路 delta-sigma 的比较（ $\Delta \Sigma $ ) 当分辨率高于 12 位时，IADC 显示我们提出的 IADC 的理论品质因数 (FoM) 高 3 dB。我们提出的系统分析可用于估计基于放大器的 NS-SAR ADC 的功率界限 $\Delta \Sigma $ 或采用各种 CMOS 技术设计的多级和多步拓扑的增量模式。报告的分析结果由先前报告的实施的实验结果证实。