This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8–b weight to 119.2 TOPS/W for 2-b weight.

中文翻译：

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用于精确可扩展 DNN 加速器的具有双 SRAM 架构的电荷域可扩展权重内存计算宏

本文介绍了一种用于可精确扩展的深度神经网络加速器的电荷域内存计算 (IMC) 宏。建议的带有耦合电容器的双 SRAM 单元结构支持具有可变精度符号权重的电荷域乘法和累加 (MAC) 操作。与仅支持二进制神经网络或数字计算多位权重 MAC 操作的加权和的先前电荷域 IMC 宏不同，所提出的宏通过新颖的串联耦合合并实现了用于节能位可缩放 MAC 操作的模拟加权和方案。具有16-kb SRAM宏的测试芯片采用28-nm FDSOI工艺制造，测得的宏吞吐量为125.2-876.5 GOPS，权重位精度从2到8不等。该宏还实现了18.4 TOPS的能效/W 将 8-b 权重设为 119。