With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. To mitigate the effects of SEUs, we propose a soft-error-immune read-stability-improved (SIRI) SRAM cell. To assess the performance of the proposed cell, it is compared with other soft-error-immune SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, RHBD14T and RSP14T. Simulation results confirm that the detrimental effects of SEUs do not alter the state of SIRI as all the sensitive nodes can reattain their initial states after being impacted by an SEU. The cell can also recover from single-event multi-node upsets (SEMNUs) that occur at its storage node-pair. Moreover, the storage nodes of the proposed cell are isolated from the bitlines during read operation. Hence, it exhibits the highest read stability. The write ability and write delay of SIRI are also superior to those of the majority of the comparison cells, and it consumes much lower hold power than many of the conventional SRAM cells. All these improvements are brought about only at the expense of a slightly longer read delay.

中文翻译：

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软错误免疫读取稳定性改进的 SRAM，可在空间应用中实现多节点翻转容错


随着晶体管尺寸和电源电压的大幅缩小，敏感节点的临界电荷正在迅速减少。因此，当这些深亚微米器件用于太空环境中的存储单元时，单粒子翻转（SEU）（也称为软错误）会对单元的可靠性构成巨大威胁。为了减轻 SEU 的影响，我们提出了一种软错误免疫读取稳定性改进 (SIRI) SRAM 单元。为了评估所提出的单元的性能，将其与其他软错误免疫 SRAM 单元（即 QUCCE12T、WE-QUATRO、RHPD12T、RHBD14T 和 RSP14T）进行了比较。仿真结果证实，SEU 的有害影响不会改变 SIRI 的状态，因为所有敏感节点在受到 SEU 影响后都可以恢复其初始状态。该单元还可以从其存储节点对发生的单事件多节点干扰 (SEMNU) 中恢复。此外，所提出的单元的存储节点在读取操作期间与位线隔离。因此，它表现出最高的读取稳定性。 SIRI 的写入能力和写入延迟也优于大多数比较单元，并且其消耗的保持功率比许多传统 SRAM 单元低得多。所有这些改进都是以稍长的读取延迟为代价的。