Sparse code multiple access (SCMA) is a promising technology for the development of wireless communication, which supports a large number of overloading users and enjoys high spectral efficiency. However, conventional SCMA decoders suffer very high complexity in implementations. Changing the updating scheme is a superior approach to reduce complexity, which guarantees the updated information immediately join in the following message propagating of the current iteration and accelerates the decoding convergence. In this paper, a row-layered message passing algorithm (MPA) is proposed, which offers a good trade-off between the hardware complexity and the bit error rate (BER) performance. Simulation results show that the proposed decoder saves 66.7% computation complexity compared with the original MPA with the similar BER performance. Pipelining and folding technology are adopted in VLSI implementations. The synthesis results with 45-nm CMOS technology show that the proposed decoder can achieve higher hardware efficiency and throughput under a high frequency than the existing decoders, achieving 1777.78 Mb/s throughput with 1.112 mm2 area consumption.

中文翻译：

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用于稀疏代码多址访问的高效行层解码器


稀疏码多址接入(SCMA)是无线通信发展的一项很有前景的技术，它支持大量的过载用户，并享有较高的频谱效率。然而，传统的SCMA解码器在实现上具有非常高的复杂性。改变更新方案是降低复杂度的一种较好的方法，可以保证更新后的信息立即加入当前迭代的后续消息传播中，加速解码收敛。本文提出了一种行分层消息传递算法（MPA），该算法在硬件复杂性和误码率（BER）性能之间提供了良好的权衡。仿真结果表明，与具有相似BER性能的原始MPA相比，所提出的解码器节省了66.7%的计算复杂度。 VLSI实现中采用了流水线和折叠技术。采用45 nm CMOS技术的综合结果表明，与现有解码器相比，所提出的解码器在高频下能够实现更高的硬件效率和吞吐量，以1.112 mm2的面积消耗实现1777.78 Mb/s的吞吐量。