To reduce energy consumption, it is possible to operate embedded systems at sub-nominal conditions (e.g., reduced voltage, limited eDRAM refresh rate) that can introduce bit errors in their memories. These errors can affect the stored values of convolutional neural network (CNN) weights and activations, compromising their accuracy. In this article, we introduce Embedded Ensemble CNNs (E ² CNNs), our architectural design methodology to conceive ensembles of convolutional neural networks to improve robustness against memory errors compared to a single-instance network. Ensembles of CNNs have been previously proposed to increase accuracy at the cost of replicating similar or different architectures. Unfortunately, state-of-the-art (SoA) ensembles do not suit well embedded systems, in which memory and processing constraints limit the number of deployable models. Our proposed architecture solves that limitation applying SoA compression methods to produce an ensemble with the same memory requirements of the original architecture, but with improved error robustness. Then, as part of our new E ² CNNs design methodology, we propose a heuristic method to automate the design of the voter-based ensemble architecture that maximizes accuracy for the expected memory error rate while bounding the design effort. To evaluate the robustness of E ² CNNs for different error types and densities, and their ability to achieve energy savings, we propose three error models that simulate the behavior of SRAM and eDRAM operating at sub-nominal conditions. Our results show that E ² CNNs achieves energy savings of up to 80 percent for LeNet-5, 90 percent for AlexNet, 60 percent for GoogLeNet, 60 percent for MobileNet and 60 percent for an optimized industrial CNN, while minimizing the impact on accuracy. Furthermore, the memory size can be decreased up to 54 percent by reducing the number of members in the ensemble, with a more limited impact on the original accuracy than obtained through pruning alone.

中文翻译：

---

E ² CNN：卷积神经网络的集合，以提高对边缘计算设备中内存错误的鲁棒性

为了降低能耗，可以在次标称条件下（例如，降低电压、有限的 eDRAM 刷新率）运行嵌入式系统，这可能会在其内存中引入位错误。这些错误会影响卷积神经网络 (CNN) 权重和激活的存储值，从而影响其准确性。在本文中，我们介绍了 Embedded Ensemble CNNs (E ² CNNs），我们的架构设计方法，用于构思卷积神经网络的集合，以提高与单实例网络相比对内存错误的鲁棒性。之前已经提出了 CNN 的集成，以复制相似或不同的架构为代价来提高准确性。不幸的是，最先进的 (SoA) 集成并不适合嵌入式系统，其中内存和处理限制限制了可部署模型的数量。我们提出的架构解决了应用 SoA 压缩方法产生与原始架构具有相同内存要求但具有改进的错误鲁棒性的集成的限制。然后，作为我们新 E ^{2 的一部分} 在 CNN 设计方法中，我们提出了一种启发式方法来自动设计基于投票者的集成架构，该架构在限制设计工作的同时最大限度地提高预期内存错误率的准确性。为了评估 E ² CNN 对不同错误类型和密度的鲁棒性 及其实现节能的能力，我们提出了三个错误模型来模拟 SRAM 和 eDRAM 在次标称条件下运行的行为。我们的结果表明，E ² CNN 实现了 LeNet-5 高达 80%、AlexNet 90%、GoogLeNet 60%、MobileNet 60% 和优化工业 CNN 60% 的节能，同时最大限度地减少了对准确性的影响。此外，通过减少集成中的成员数量，可以将内存大小减少多达 54%，对原始精度的影响比单独通过修剪获得的影响更有限。