Purpose

This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.

Design/methodology/approach

The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.

Findings

Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.

Originality/value

The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

中文翻译：

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使用 PMOS 作为存取晶体管的具有增强读取 SNM 的 7T SRAM 单元的设计和数学分析

目的

这项工作是针对笔记本电脑、手机和掌上电脑等低功耗节能应用提出的。在这项研究中，P 沟道金属氧化物半导体 (PMOS) 被用作 7 个晶体管 (7 T) 静态随机存取存储器 (SRAM) 单元中的存取晶体管，以及理论静态噪声容限 (SNM) 分析建议的单元格也被执行。一个单元使用 7 T 设计，由 4 个 PMOS 和 3 个 NMOS 组成。在本文中，写入和保持 SNM 被寻址，读取 SNM 也被计算用于提议的 7 T SRAM 单元。

设计/方法/方法

作者已将 N 沟道金属氧化物半导体 (NMOS) 访问晶体管替换为 PMOS 访问晶体管，这会导致正确的数据线恢复并提供所需的耦合。如果读取操作执行过于频繁，可能会发生错误，可能是使用 NMOS 传输门。这会导致数据线恢复不当。相反，通过使用 PMOS 作为传输门，可以降低读取操作所需的时间。正如我们所知，PMOS 晶体管的迁移率 (µ) 很低，因此作者将这一特性用于提议的设计。当低信号施加到其控制栅极时，PMOS 晶体管在用作传输门时会产生所需的耦合。

发现

所提出的电路中使用了反馈开关晶体管，它在写操作中起着重要作用。当建议的单元在读取模式下工作时，该晶体管处于关闭状态，PMOS 用作存取晶体管。这有助于降低功率。这项工作是在 cadence virtuoso 环境中使用 UMC 40 nm 技术节点进行模拟的。模拟结果表明，与报告的7T和6T相比，写入功耗分别为51.54%和61.17%，分别保持25.68%和48.93%的功耗。

原创性/价值

当 PMOS 用作存取晶体管时，所提出的 7 T SRAM 单元可在较低电压下提供适当的数据线恢复。这种技术的功耗非常低，最适合低功耗应用。