A superior figure-of-merit (FoM) 1200 V class 4H-SiC trench MOSFET with p + shielding region partially surrounded by the buried n region is proposed in this paper. The buried n region is introduced to restrain the lateral extension of the depletion layer formed by p + shielding region at the quasi-saturation (QS) state, which leads to a significant improvement of the transfer and forward characteristics. The buried n region expands the current path in the JFET region, decreasing the JFET resistance and improving the maximum transconductance (g_fs). Thereby the QS effect of the device with p + shielding region caused by the JFET region gets effectively suppressed. Moreover, the influences of the parameters of the buried n region on the breakdown voltage (BV), the dynamic characteristic and the gate oxide reliability are investigated to determine the optimized device cell structure. Simulation results show that the specific on-resistance (R_on,sp) of the proposed device with the optimized buried n region is decreased by 19.3%, reaching a value of 1.63 mΩ•cm². The maximum g_fs is enhanced by 30%. The FoM₁ (FoM₁ = BV²/R_on,sp) is utilized to judge the trade-off relationship between the BV and the R_on,sp, which is improved by 20.5%, reaching 1.45 kV²/mΩ•cm².

本文提出了一种优异的品质因数 (FoM) 1200 V 类 4H-SiC 沟槽 MOSFET，其 p + 屏蔽区部分被埋入 n 区包围。引入埋入n区以抑制准饱和（QS）状态下p+屏蔽区形成的耗尽层的横向扩展，从而显着改善转移和正向特性。埋入 n 区扩展了 JFET 区中的电流路径，降低了 JFET 电阻并提高了最大跨导 (g _fs）。从而有效抑制了由JFET区域引起的具有p+屏蔽区域的器件的QS效应。此外，还研究了埋入 n 区的参数对击穿电压 (BV)、动态特性和栅极氧化物可靠性的影响，以确定优化的器件单元结构。仿真结果表明，所提出的具有优化埋入n区的器件的比导通电阻(R _on,sp )降低了19.3%，达到1.63 mΩ•cm ^{2 的值}。最大 g _fs提高了 30%。FoM ₁ (FoM ₁  = BV ² /R _on,sp )用于判断BV和R之间的权衡关系_on,sp提高了20.5%，达到1.45 kV ² /mΩ•cm ²。