Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

中文翻译：

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用于高速缓存存储器的紧凑型高速基于 Hsiao 的 SEC-DED 编解码器

最近，人们对用于保护存储单元免受软错误影响的多位纠错码 (ECC) 的兴趣不断增加，这也可以提高存储系统的可靠性。单纠错和双错误检测 (SEC-DED) 码通常用于许多高速存储系统中。在本文中，基于 Hsiao 的 SEC-DED 代码基于奇偶校验矩阵和纠错逻辑中采用的两种优化算法进行了优化。与 Hsiao 码相比，SEC-DED 编解码器的理论面积复杂度需要最大 49.29%、18.64% 和 49.21% [MY Hsiao，A 类最优最小奇数列 SEC-DED 码，IBM J. 水库。开发。 14(1970) 395–401]，Reviriego等。代码 [P. Reviriego、S. Pontarelli、JA Maestro 和 M. Ottavi，一种构建低延迟单纠错码仅用于保护数据位的方法，IEEE Trans。计算机辅助设计。积分。电路系统。 32(2013) 479–483] 和刘等。代码 [S. Liu、P. Reviriego、L. Xiao 和 JA Maestro，一种在 SEC-DED 保护存储器中的双重错误下恢复关键位的方法，微电子。可靠。 73（2017）92-96]，分别。所提出的编解码器在现场可编程门阵列 (FPGA) 和 ASIC 平台中都设计和实现。合成的 SEC-DED 编解码器需要的 LUT 比原始 Hsiao 代码少 31.14%。优化的编解码器比现有的相关编解码器更快，而不影响其功耗。这些紧凑且速度更快的 SEC-DED 编解码器用于高速缓存以提高可靠性。