Two-dimensional convolution plays a fundamental role in different image processing applications. Image convolving with different kernel sizes enriches the overall performance of image processing applications. In this regard, it is necessary to design of reconfigurable convolver with respect to desired kernel sizes list. In this paper, a novel approach is presented for implementation of an area-efficient reconfigurable convolver with appropriate throughput and convolution computational time for an arbitrary kernel size list. This approach is based on the adjustment of logical blocks arrangement in the conventional convolvers. The feasibility and benefits of the proposed approach are demonstrated through a case study of the design implementation on an FPGA platform using the XILINX ISE software. Compared to the well-known reconfigurable convolvers, the proposed design significantly reduces convolution computational time and improves throughput with a reasonable number of hardware resources. For instance, the proposed reconfigurable convolver only requires 0.38 ms to perform a 3 × 3 convolution on a 268 × 460 image with 8-bit pixels and only occupies 455 slices resource of Xilinx Virtex-4 (XC4VLX25) FPGA, in which the throughput of 324 million outputs per second (MOPS) is provided with 81 MHz clock frequency for kernel size of 3 × 3. On average, the MPOS of the proposed approach is approximately improved by 43.13% in relation to the other considered alternatives. Experimental results confirm that the proposed reconfigurable convolver is a very competitive design among the alternative reconfigurable convolvers.

二维卷积在不同的图像处理应用中扮演着重要的角色。使用不同内核大小的图像卷积丰富了图像处理应用程序的整体性能。在这方面，有必要针对所需的内核大小列表设计可重构卷积器。在本文中，提出了一种新方法，用于实现具有适当吞吐量和卷积计算时间的区域高效可重构卷积器，适用于任意内核大小列表。这种方法是基于对传统卷积器中逻辑块排列的调整。通过使用 XILINX ISE 软件在 FPGA 平台上进行设计实现的案例研究，证明了所提出方法的可行性和优势。与众所周知的可重构卷积器相比，所提出的设计显着减少了卷积计算时间，并通过合理数量的硬件资源提高了吞吐量。例如，所提出的可重构卷积器只需 0.38 ms 即可在 8 位像素的 268 × 460 图像上执行 3 × 3 卷积，并且仅占用 Xilinx Virtex-4 (XC4VLX25) FPGA 的 455 个切片资源，其中吞吐量为每秒 3.24 亿输出 (MOPS) 以 81 MHz 时钟频率提供，内核大小为 3 × 3。平均而言，与其他考虑的替代方案相比，所提出方法的 MPOS 大约提高了 43.13%。实验结果证实，所提出的可重构卷积器是替代可重构卷积器中极具竞争力的设计。