Microprocessors are widely used in space applications. ARM processors fabricated with FDSOI technologies are promising for future space programs. However, radiation-hardening approaches can greatly affect the resource overhead and performance. These hardening techniques need to be evaluated at system level to better understand their effectiveness, especially for modern CMOS technologies. In this paper, two ARM® Cortex® M0 cores, a reference core and a hardened core were implemented on the same die in a 28-nm FDSOI technology. The reference core was designed with components from the standard cell library, while the other one was implemented with hardened DICE flip-flops. Both of the cores shared the same on-chip TMR-protected SRAM. Heavy ion experiments showed that the error cross section of the core with DICE flip-flops was about 2 times smaller at LET of 40 MeV·cm²·mg⁻¹. This suggests that the contribution from logic circuits in the microprocessor cores also need to be considered for better error reduction.

微处理器广泛用于空间应用。使用 FDSOI 技术制造的 ARM 处理器有望用于未来的太空计划。然而，抗辐射方法会极大地影响资源开销和性能。这些强化技术需要在系统级别进行评估，以更好地了解它们的有效性，尤其是对于现代 CMOS 技术。在本文中，两个 ARM® Cortex® M0 内核、一个参考内核和一个硬化内核采用 28 纳米 FDSOI 技术在同一芯片上实现。参考内核是使用标准单元库中的组件设计的，而另一个内核是使用硬化的 DICE 触发器实现的。两个内核共享同一个受 TMR 保护的片上 SRAM。² ·mg ^-1。这表明还需要考虑微处理器内核中逻辑电路的贡献，以更好地减少错误。