Multiplications have been commonly conducted in quantized CNNs, filters, and reconfigurable cores, and so on, which are widely deployed in mobile and embedded applications. Most multipliers are designed to perform multiplications with symmetric bit-widths, i.e., n - by n -bit multiplication. Such features would cause extra area overhead and performance loss when m - by n -bit multiplications ( m > n ) are deployed in the same hardware design, resulting in inefficient multiplication operations. It is highly desired and challenging to propose a reconfigurable multiplier design to accommodate operands with both symmetric and asymmetric bit-widths. In this work, we propose a reconfigurable approximate multiplier to support multiplications at various precisions, i.e., bit-widths. Unlike prior works of approximate adders assuming a uniform weight distribution with bit-wise independence, scenarios like a quantized CNN may have a centralized weight distribution and hence follow a Gaussian-like distribution with correlated adjacent bits. Thus, a new block-based approximate adder is also proposed as part of the multiplier to ensure energy-efficient operation with an awareness of the bit-wise correlation. Our experimental results show that the proposed approximate adder significantly reduces the error rate by 76% to 98% over a state-of-the-art approximate adder for Gaussian-like distribution scenarios. Evaluation results show that the proposed multiplier is 19% faster and 22% more power saving than a Xilinx multiplier IP at the same bit precision and achieves a 23.94-dB peak signal-to-noise ratio, which is comparable to the accurate one of 24.10 dB when deployed in a Gaussian filter for image processing tasks.

中文翻译：

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非对称位宽有符号乘法的可重构乘法器

乘法通常在量化的 CNN、滤波器和可重构核等中进行，它们广泛部署在移动和嵌入式应用程序中。大多数乘法器旨在执行具有对称位宽的乘法，即n- 经过n位乘法。这些功能会导致额外的面积开销和性能损失米- 经过n位乘法（米>n) 部署在相同的硬件设计中，导致乘法运算效率低下。提出一种可重新配置的乘法器设计以适应具有对称和非对称位宽的操作数是非常需要和具有挑战性的。在这项工作中，我们提出了一种可重新配置的近似乘法器，以支持各种精度（即位宽）的乘法。与先前的近似加法器工作假设具有位独立的均匀权重分布不同，像量化 CNN 这样的场景可能具有集中的权重分布，因此遵循具有相关相邻位的类高斯分布。因此，还提出了一种新的基于块的近似加法器作为乘法器的一部分，以确保在了解逐位相关的情况下进行节能操作。我们的实验结果表明，与用于类高斯分布场景的最先进的近似加法器相比，所提出的近似加法器将错误率显着降低了 76% 至 98%。评估结果表明，在相同位精度下，所提出的乘法器比 Xilinx 乘法器 IP 快 19%，省电 22%，峰值信噪比达到 23.94 dB，与 24.10 的精确值相当部署在用于图像处理任务的高斯滤波器中时的 dB。