Multi-core hardware integrates multiple processing cores onto a single chip. To reduce costs and to improve performance in the average case, these cores typically share a number of hardware resources, including the interconnect, parts of the memory hierarchy (e.g., caches), and main memory. By contending for these shared hardware resources, tasks executing on one core can potentially interfere with tasks executing on another core, substantially increasing their execution times. Contention for shared hardware resources thus poses a significant challenge in the development of predictable hard real-time systems running on multi-core platforms. Three concepts that are useful in a discussion of the real-time behaviour of multicore systems are Timing Composability, Timing Compositionality, and Timing Predictability. Timing Composability means that the timing properties derived for individual tasks studied separately (i.e., executing alone) still hold after their composition with other tasks, for example when they are run with the other tasks executing on the other cores. Timing Composability is highly valued from an industry perspective as it enables incremental development and verification. Different teams can develop and verify different sub-systems, in the knowledge that their timing behaviour will not change when integrated into the complete system. Timing Compositionality means that the timing properties of interest, for example the Worst-Case Execution Time (WCET) of a task can be determined via a decomposition into constituent parts (for example, the worst-case processing time plus the worst-case delays waiting for the bus plus the worse-case latencies waiting for memory). Timing Compositionality is a key property required by much of the research on timing analysis and on integrated timing and schedulability analysis for multi-core platforms, and indeed by WCET analysis in general. Systems that are not timing compositional exhibit timing anomalies meaning that the (local) worst-case behaviour of some resource does not lead to the overall (global) worst-case execution time. Systems with timing anomalies are much

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客座社论：关于可预测多核系统的特刊

多核硬件将多个处理核心集成到单个芯片上。在一般情况下，为了降低成本并提高性能，这些内核通常共享许多硬件资源，包括互连、部分存储器层次结构（例如，高速缓存）和主存储器。通过争夺这些共享硬件资源，在一个内核上执行的任务可能会干扰在另一个内核上执行的任务，从而显着增加它们的执行时间。因此，对共享硬件资源的争用对在多核平台上运行的可预测硬实时系统的开发提出了重大挑战。在讨论多核系统的实时行为时，三个有用的概念是时序可组合性、时序组合性和时序可预测性。时序可组合性意味着为单独研究（即单独执行）的单个任务导出的时序属性在与其他任务组合后仍然保持，例如当它们与在其他内核上执行的其他任务一起运行时。从行业角度来看，时序可组合性受到高度重视，因为它支持增量开发和验证。不同的团队可以开发和验证不同的子系统，因为它们的时序行为在集成到完整系统中时不会改变。时序组合性意味着感兴趣的时序属性，例如任务的最坏情况执行时间 (WCET) 可以通过分解为组成部分（例如，最坏情况下的处理时间加上最坏情况下等待总线的延迟加上最坏情况下等待内存的延迟）。时序组合性是许多关于时序分析和多核平台的集成时序和可调度性分析的研究以及一般的 WCET 分析所需的关键属性。不是时序组合的系统表现出时序异常，这意味着某些资源的（本地）最坏情况行为不会导致整体（全局）最坏情况执行时间。具有时序异常的系统很多 不是时序组合的系统表现出时序异常，这意味着某些资源的（本地）最坏情况行为不会导致整体（全局）最坏情况执行时间。具有时序异常的系统很多 不是时序组合的系统表现出时序异常，这意味着某些资源的（本地）最坏情况行为不会导致整体（全局）最坏情况执行时间。具有时序异常的系统很多