Multi-threshold voltage complementary metal-oxide semiconductor (MTCMOS) technology finds a wide variety of applications in reducing the subthreshold-leakage current in both combinational and sequential circuits. This is due to the fact that slightly increasing the threshold voltage causes a dramatic decrease in the subthreshold-leakage current. One of the most important applications of the MTCMOS technology is the use of a sleep transistor with high threshold voltage. However, the decision on the sizing of the sleep transistor is a critical issue because there are various trade-offs that the designer must face with this respect. In this paper, the area, the static and dynamic-power consumption, and the time delay are investigated with respect to the aspect ratio of the sleep transistor with compact-form expressions derived for them. Accordingly, the optimal size of the sleep transistor is determined quantitatively. In addition, a realistic figure of merit (FOM) that takes into account the contradicting parameters when sizing the sleep transistor is introduced and verified by simulations. The results are discussed for various cases of the logic circuit at hand. The results obtained are also verified by simulation adopting the Berkeley predictive technology model (BPTM) of the 45 nm, 32 nm, and 22 nm CMOS technologies with power-supply voltages, V_DD, equal to 1 V, 0.9 V, and 0.8 V, respectively.

多阈值电压互补金属氧化物半导体 (MTCMOS) 技术在降低组合电路和时序电路中的亚阈值泄漏电流方面具有广泛的应用。这是因为稍微增加阈值电压会导致亚阈值泄漏电流急剧下降。MTCMOS 技术最重要的应用之一是使用具有高阈值电压的休眠晶体管。然而，关于睡眠晶体管尺寸的决定是一个关键问题，因为设计人员在这方面必须面对各种权衡。在本文中，面积、静态和动态功耗以及时间延迟相对于睡眠晶体管的纵横比进行了研究，并为其导出了紧凑形式的表达式。因此，睡眠晶体管的最佳尺寸是定量确定的。此外，一个现实的品质因数（FOM ) 在确定睡眠晶体管的大小时考虑了相互矛盾的参数，并通过模拟进行了验证。讨论了手头逻辑电路的各种情况的结果。所得结果还通过采用 45 nm、32 nm 和 22 nm CMOS 技术的 Berkeley 预测技术模型 (BPTM) 进行仿真验证，电源电压V _DD等于 1 V、0.9 V 和 0.8 V ， 分别。