This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated integration time. A 13-bit 312.5-MS/s two-stage pipelined SAR ADC employing the presented technique is fabricated in a 28-nm process. At a sampling rate of 312.5 MS/s, the prototype ADC achieves a 65.1-dB SNDR and a Walden FoM of 13.95 fJ/conversion-step with an over Nyquist input. Less than 1-dB SNDR variation are obtained for supply voltage varying within ±60 mV and the temperature varying from -40 °C to 120 °C, respectively.

中文翻译：

---

具有基于开环积分器的剩余放大器和增益稳定积分时间生成功能的 13 位 312.5MS/s 流水线 SAR ADC


本文介绍了一种增益稳定积分时间生成技术，适用于利用基于开环积分器的剩余放大器 (RA) 的流水线逐次逼近寄存器 (SAR) 模数转换器 (ADC)。通过自适应调整生成的积分时间的长度，可以减轻 RA 在不同工艺、电压和温度 (PVT) 条件下的增益变化。采用所提出技术的 13 位 312.5 MS/s 两级流水线 SAR ADC 采用 28 nm 工艺制造。在采样率为 312.5 MS/s 时，原型 ADC 可实现 65.1 dB SNDR 和 13.95 fJ/转换步的 Walden FoM，并具有超奈奎斯特输入。当电源电压在 ±60 mV 范围内变化以及温度在 -40 °C 至 120 °C 范围内变化时，SNDR 变化小于 1 dB。