In this work, we address the synthesis problem of two-phase bundled-data asynchronous pipeline controllers, in which the insertion of buffers is essential for guaranteeing the correct handshaking operation on every pipeline stage at the expense of considerable area increase. To lighten the pipeline controllers, we introduce a new logic synthesis concept called delay path sharing and reusing , by which we can significantly reduce the amount of the costly delay buffers. Precisely, first, we propose a technique of synthesizing an asynchronous pipeline controller in a way to share delay buffers among setup timing paths on pipeline stages for minimally allocating total delay buffers. In addition, we devise an area-efficient delay circuit structure called delay path unit (DPU) by extending the proposed delay path sharing concept and propose an in-depth synthesis flow of an asynchronous pipeline controller using DPUs. Through experiments with benchmark circuits using a 45-nm cell library, it is shown that our techniques of synthesizing asynchronous pipeline controllers are able to reduce the controller area by up to 46.3%–59.4% and the leakage power by up to 33.0%–49.0% on average while retaining the same level of performance.

中文翻译：

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闪电异步管道控制器的可重用延迟路径综合


在这项工作中，我们解决了两相捆绑数据异步管道控制器的综合问题，其中缓冲区的插入对于保证每个管道阶段的正确握手操作至关重要，但代价是相当大的面积增加。为了减轻流水线控制器的重量，我们引入了一种新的逻辑综合概念，称为延迟路径共享和重用，通过它我们可以显着减少昂贵的延迟缓冲区的数量。准确地说，首先，我们提出了一种综合异步流水线控制器的技术，其方式是在流水线级上的设置时序路径之间共享延迟缓冲区，以最小化分配总延迟缓冲区。此外，我们通过扩展所提出的延迟路径共享概念，设计了一种称为延迟路径单元（DPU）的面积高效延迟电路结构，并提出了使用 DPU 的异步流水线控制器的深入综合流程。通过使用45 nm单元库的基准电路实验，表明我们的异步流水线控制器合成技术能够将控制器面积减少高达46.3%–59.4%，漏电功率减少高达33.0%–49.0 %，同时保持相同的性能水平。