Decision trees (DTs) are profusely used in machine learning (ML) applications on account of their fast execution and high interpretability. As DT training is time-consuming, in this brief, we proposed a hardware training accelerator to speedup the training process. The proposed training accelerator is implemented on the field-programmable gate array (FPGA) having a maximum operating frequency of 62 MHz. The proposed architecture uses a combination of parallel execution for training time reduction and pipelined execution to minimize resource consumption. For a given design, the proposed hardware implementation is found to be at least 14× faster than the C-based software implementation. Moreover, the proposed architecture can be easily retrained for the next set of data using a single RESET signal. This on-the-go training makes the hardware versatile for any kind of application.

中文翻译：

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两种方法决策树的训练加速器


决策树 (DT) 因其快速执行和高可解释性而广泛用于机器学习 (ML) 应用程序。由于 DT 训练非常耗时，因此在本文中，我们提出了一种硬件训练加速器来加速训练过程。所提出的训练加速器在最大工作频率为 62 MHz 的现场可编程门阵列 (FPGA) 上实现。所提出的架构结合使用并行执行来减少训练时间和流水线执行来最大限度地减少资源消耗。对于给定的设计，建议的硬件实现比基于 C 的软件实现至少快 14 倍。此外，所提出的架构可以使用单个 RESET 信号轻松地针对下一组数据进行重新训练。这种移动培训使硬件能够适应任何类型的应用。