This brief presents a three-stage comparator and its modified version to improve the speed and reduce the kickback noise. Compared to the traditional two-stage comparators, the three-stage comparator in this work has an extra amplification stage, which enlarges the voltage gain and increases the speed. Unlike the traditional two-stage structure that uses pMOS input pair in the regeneration stage, the three-stage comparator makes it possible to use nMOS input pairs in both the regeneration stage and the amplification stage, further increasing the speed. Furthermore, in the proposed modified version of three-stage comparator, a CMOS input pair is adopted at the amplification stage. This greatly reduces the kickback noise by canceling out the nMOS kickback through the pMOS kickback. It also adds an extra signal path in the regeneration stage, which helps increase the speed further. For easy comparison, both the conventional two-stage and the proposed three-stage comparators are implemented in the same 130-nm CMOS process. Measured results show that the modified version of three-stage comparator improves the speed by 32%, and decreases the kickback noise by ten times. This improvement is not at the cost of increased input referred offset or noise.

中文翻译：

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一种快速低反冲的三级比较器及其改进版本


本简介介绍了一个三级比较器及其改进版本，以提高速度并减少反冲噪声。与传统的两级比较器相比，本工作中的三级比较器多了一个放大级，扩大了电压增益并提高了速度。与传统的在再生级使用pMOS输入对的两级结构不同，三级比较器使得在再生级和放大级都可以使用nMOS输入对，进一步提高了速度。此外，在所提出的三级比较器的修改版本中，放大级采用了 CMOS 输入对。这通过 pMOS 反冲抵消了 nMOS 反冲，从而大大降低了反冲噪声。它还在再生阶段添加了额外的信号路径，这有助于进一步提高速度。为了便于比较，传统的两级比较器和所提出的三级比较器都是在相同的 130 nm CMOS 工艺中实现的。测量结果表明，改进后的三级比较器的速度提高了32%，反冲噪声降低了10倍。这种改进并不以增加输入参考偏移或噪声为代价。