In this article, a novel method to suppress differential-to-common mode conversion noise in differential serpentine delay microstrip lines (DSDMLs) is proposed. To suppress the remnant mode conversion noise, embedded coupled lines are adopted in the parallel traces section of DSDMLs. Embedded coupled lines can minimize the timing delay between even- and odd-modes in the parallel traces section. In specific dimensions, embedded coupled lines propagate even- and odd-mode signals with the same velocity without changing the differential-mode impedance, so DSDMLs with embedded coupled lines can suppress differential-to-common mode conversion noise without degrading differential-mode signal quality. In simulations, the proposed DSDMLs exhibit about 93.0% suppression of the peak common-mode conversion voltage compared with conventional DSDMLs, regardless of the length of the parallel traces section of DSDMLs. The performance of our proposed DSDMLs is verified by conducting measurements with millimeter-scale test boards in the frequency and time domains. The test board exhibited 78.7% suppression of common-mode conversion noise without degrading the differential insertion loss compared with conventional DSDMLs. Simulations and measurement results exhibited good agreement.

中文翻译：

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差分蛇形延迟微带线中嵌入耦合线的共模转换噪声抑制

在本文中，提出了一种抑制差分蛇形延迟微带线 (DSDML) 中差分到共模转换噪声的新方法。为了抑制残余模式转换噪声，DSDML 的平行走线部分采用了嵌入式耦合线。嵌入式耦合线可以最大限度地减少平行走线部分偶数模式和奇数模式之间的时序延迟。在特定的维度上，嵌入式耦合线以相同的速度传播偶模和奇模信号，而不会改变差模阻抗，因此嵌入式耦合线的 DSDML 可以抑制差模到共模转换的噪声，而不会降低差模信号质量. 在模拟中，与传统的 DSDML 相比，所提出的 DSDML 表现出约 93.0% 的峰值共模转换电压抑制，无论 DSDML 的平行走线部分的长度如何。我们提出的 DSDML 的性能通过在频域和时域中使用毫米级测试板进行测量来验证。与传统 DSDML 相比，该测试板在不降低差分插入损耗的情况下对共模转换噪声进行了 78.7% 的抑制。模拟和测量结果显示出良好的一致性。