Automated formal verification techniques, based on model checking and theorem proving, usually have scalability issues for contemporary digital circuits. On the other hand, interactive theorem provers can overcome this issue, by verifying circuits using universally quantified variables, at the cost of significant skilled guidance. Leveraging upon the complimentary nature of the techniques, this paper presents a hybrid model checking - theorem proving approach for the formal functional verification of digital circuits (HVoC). The main idea is to first use a higher-order-logic theorem prover to replace the structural (RTL or gate level) implementations of the combinational modules with their, formally verified, corresponding behavior and then verify the complete behavioral implementation using a model checker. This kind of a 2-step process not only reduces the computational complexity, but, is also quite effective in terms of counterexample generation time. Our experiments on some benchmarks show an average \(50\%\) reduction in analysis time.

基于模型检查和定理证明的自动化形式验证技术通常存在当代数字电路的可扩展性问题。另一方面，交互式定理证明者可以通过使用普遍量化的变量验证电路来克服这个问题，但需要大量熟练的指导。利用这些技术的互补性质，本文提出了一种混合模型检查 - 定理证明方法，用于数字电路的形式功能验证(HVoC)。主要思想是首先使用高阶逻辑定理证明器将组合模块的结构（RTL 或门级）实现替换为其形式化验证的相应行为，然后使用模型检查器验证完整的行为实现。这种两步过程不仅降低了计算复杂度，而且在反例生成时间方面也非常有效。我们在一些基准测试中的实验表明，分析时间平均减少了\(50\%\)。