The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, VDD collapse and 9T UV SRAM, respectively.

中文翻译：

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使用负位线写入辅助技术和用于高速应用的独立读取端口设计和分析 SRAM 单元

当今的电子产品具有存储数据的半导体存储设备。静态随机存取存储器 (SRAM) 是一种易失性存储器，由于更高的速度和更低的功耗，通常比动态随机存取存储器 (DRAM) 更受欢迎。然而，在技术节点按比例缩小时，SRAM 中的漏电流通常会增加并降低其性能。为了解决这个问题，电压缩放是首选，这随后会影响 SRAM 的稳定性和延迟。因此，本文提出了一种负位线（NBL）写辅助电路，用于提高写能力，而单独的（隔离）读缓冲电路用于提高读稳定性。除此之外，建议的设计使用尾部（堆叠）晶体管来降低整体静态功耗并保持保持稳定性。在写入静态噪声容限 (WSNM)、写入延迟、读取静态噪声容限 (RSNM) 和其他参数方面，已将提议的设计与最先进的工作进行了比较。据观察，与传统的 6T SRAM 单元 NBL 相比，WSNM 改善了 48%、11%、19% 和 32.4%，而写入延迟减少了 33%、39%、48% 和 22% ,五DD分别为collapse和9T UV SRAM。