In this paper, we first investigate the noise model for 2D-TMD monolayer molybdenum disulfide (${\text{MoS}}_2$) transistors. With a proposed noise model, simulation results of low-frequency noise for ${\text{MoS}}_2$ transistors agree well with measurement data. Then, in order to evaluate potential ${\text{MoS}}_2$-based circuits and explore design space, we utilize the behavior and noise models of monolayer ${\text{MoS}}_2$ transistors to analyze the phase noise of LC voltage controlled oscillators (LC VCOs). According to the $g_m/I{}_D$ concept, we develop an analytical design and optimization methodology for monolayer ${\text{MoS}}_2$ based LC VCOs. For a given circuit-level design specification, the proposed design methodology can effectively balance the phase noise and current consumption. Four design examples of ${\text{MoS}}_2$-based LC VCOs are guided using the proposed design methodology and are verified by HSPICE simulations. Compared with the HSPICE simulation results, the calculated noise phase using our proposed analytical design methodology achieves at least 95% accuracy. Finally, we design optimized LC VCO circuits with monolayer ${\text{MoS}}_2$ transistors and silicon transistors, respectively, to compare their performance. Various results reveal that the phase noise and figure-of-merit of monolayer ${\text{MoS}}_2$-based LC VCOs are about 10 dB better than silicon-based designs. It indicates monolayer ${\text{MoS}}_2$ transistor is promising to replace silicon in analog/RF circuits for better noise performance or lower power consumption.

在本文中，我们首先研究了 2D-TMD 单层二硫化钼的噪声模型（${\text{硫化钼}}_2$) 晶体管。使用建议的噪声模型，低频噪声的仿真结果为${\text{硫化钼}}_2$晶体管与测量数据非常吻合。然后，为了评估潜力${\text{硫化钼}}_2$基于电路和探索设计空间，我们利用单层的行为和噪声模型 ${\text{硫化钼}}_2$晶体管来分析 LC 压控振荡器 (LC VCO) 的相位噪声。根据$G_{米}/\mathrm{一世}{}_D$ 概念，我们开发了单层分析设计和优化方法 ${\text{硫化钼}}_2$基于 LC VCO。对于给定的电路级设计规范，所提出的设计方法可以有效地平衡相位噪声和电流消耗。四个设计实例${\text{硫化钼}}_2$基于 LC VCO 使用建议的设计方法进行指导，并通过 HSPICE 仿真进行验证。与 HSPICE 仿真结果相比，使用我们提出的分析设计方法计算的噪声相位至少达到 95% 的准确度。最后，我们设计了优化的单层 LC VCO 电路${\text{硫化钼}}_2$晶体管和硅晶体管，分别比较它们的性能。各种结果表明，单层的相位噪声和品质因数${\text{硫化钼}}_2$基于 LC VCO 的性能比基于硅的设计好大约 10 dB。表示单层${\text{硫化钼}}_2$ 晶体管有望取代模拟/射频电路中的硅，以获​​得更好的噪声性能或更低的功耗。