This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture.

中文翻译：

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改进的 FPGA 中的冗余二进制加法器实现

本文介绍了利用FPGA平台中的正负编码规则改进冗余二进制加法器（IRBA）的设计。所提出的设计使用现成的标准硬件模块处理负二进制 (IEN) 和正二进制数的反向编码以获得加法结果。Verilog 硬件描述语言用作在 Xilinx ISE Desisn Suite 14.4 软件中综合建议架构的设计入口。该结构在 Vertex-4 xc4vfx12-12sf363 FPGA 器件上实现。与之前报告的架构的传播延迟和面积等性能参数相比，提出的 IRBA 被发现具有时间效率。