The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock. However, it can happen that a very high-performance specifications demands to abandon this paradigm and to follow an asynchronous implementative solution. The main driver forcing the use of programmable logic solutions instead of tailored Application Specific Integrated Circuits (ASIC), best suiting an asynchronous design, is the request coming from the research community and industrial R&D of fast-prototyping at low Non Recursive Engineering (NRE) costs. For instance in the case of a high-resolved Time-to-Digital Converter (TDC), a signal clocked at some hundreds of MHz implemented in FPGA allows implementing a TDC with resolution at ns. If a higher resolution is required, the signal frequency cannot be increased further and one of the aces up the designer's sleeve is the propagation delay of the logic in order to quantize the time intervals by means of a so-called Tapped Delay-Line (TDL). This implementation of TDL-based TDC in FPGAs requires special attention by the designer both in making the best use of all available resources and in foreseeing how signals propagate inside these devices. In this paper, we investigate the implementation of a high-performance TDL-TDC addressed to 28-nm 7-Series Xilinx FPGA, taking into account the comparison between different technological nodes from 65-nm to 20-nm. In this context, the term high-performance means extended dynamic-range (up to 10.3 s), high-resolution and single-shot precision (up to 366 fs and 12 ps r.m.s respectively), low differential and integral non-linearity (up to 250 fs and 2.5 ps respectively), and multi-channel capability (up to 16).

中文翻译：

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最先进的 FPGA 时间数字转换器 IP 核


现场可编程门阵列 (FPGA) 结构提出了一些限制，使得复杂的异步电路（例如时间模式 (TM) 电路）的实现几乎不可行。特别是，在可编程逻辑 (PL) 器件（例如 FPGA）中，逻辑的操作通常与系统时钟同步。然而，可能会发生非常高性能的规范要求放弃这种范例并遵循异步实施解决方案的情况。迫使使用可编程逻辑解决方案而不是最适合异步设计的定制专用集成电路 (ASIC) 的主要驱动力是来自研究界和工业研发部门对低非递归工程 (NRE) 快速原型设计的要求成本。例如，在高分辨率时间数字转换器 (TDC) 的情况下，在 FPGA 中实现的时钟频率为数百 MHz 的信号允许实现分辨率为 ns 的 TDC。如果需要更高分辨率，则信号频率无法进一步增加，设计人员的王牌之一是逻辑的传播延迟，以便通过所谓的抽头延迟线 (TDL) 量化时间间隔）。在 FPGA 中实现基于 TDL 的 TDC 需要设计人员特别注意，既要充分利用所有可用资源，又要预见信号如何在这些器件内传播。在本文中，我们研究了针对 28 nm 7 系列 Xilinx FPGA 的高性能 TDL-TDC 的实现，同时考虑了 65 nm 到 20 nm 不同技术节点之间的比较。在这种情况下，术语“高性能”意味着扩展的动态范围（高达 10.3 s）、高分辨率和单次精度（分别高达 366 fs 和 12 ps rms）、低微分和积分非线性（分别高达 250 fs 和 2.5 ps）以及多通道功能（高达16）。