A novel current-mode analog multiplier is presented, in which a novel squarer cell and a low-power current mirror have been employed to obtain a low-power consumption circuit. The proposed architectures for the squarer cell and the multiplier circuit allow the operation both in one-quadrant and four-quadrants. The multiplier has been designed in TSMC $180nm$ CMOS technology and, to validate the circuit performance, it has been simulated using CADENCE software. In the four-quadrant configuration, post-layout simulation results demonstrate a linearity error of 0.63%, a THD of 0.41% in 1 MHz, a 3-dB bandwidth of 173 MHz with 1.4 V supply voltage, and maximum power consumption of approximately $340\mu W$. Using the one-quadrant configuration, the maximum power consumption was $55\mu W$ with 1.1 V supply voltage. The quiescent power was $75\mu W$ for the four-quadrants configuration and approximately $0\mu W$ for the one-quadrant configuration.

提出了一种新型电流模式模拟乘法器，其中采用新型平方器单元和低功耗电流镜来获得低功耗电路。所提出的用于平方器单元和乘法器电路的架构允许在一象限和四象限中运行。乘法器是在台积电设计的$180n米$CMOS 技术，为了验证电路性能，已使用 CADENCE 软件对其进行了模拟。在四象限配置中，布局后仿真结果表明线性误差为 0.63%，THD 为 0 。41% in 1 MHz，173 MHz 的 3-dB 带宽，1.4 V 电源电压，最大功耗约为$340\mu 宽$. 使用一象限配置，最大功耗为$55\mu 宽$1.1 V 电源电压。静态功率为$75\mu 宽$ 对于四象限配置和大约 $0\mu 宽$ 对于一象限配置。