With 3D-stacked DRAM architectures becoming more prevalent, it has become important to find ways to characterize and mitigate the adverse effects that can hinder their inherent access parallelism and throughput. One example of such adversities is the electromigration (EM) effects in the through-silicon vias (TSVs) of the power delivery network (PDN) of 3D-stacked DRAM architectures. Several prior works have addressed the effects of EM in TSVs of 3D integrated circuits. However, no prior work has addressed the effects of EM in the PDN TSVs on the performance and lifetime of 3D-stacked DRAMs. In this paper, we characterize the effects of EM in PDN TSVs on a Hybrid Memory Cube (HMC) architecture employing the conventional PDN design with clustered layout of power and ground TSVs. We then present a new PDN design with a distributed layout of power and ground TSVs and show that it can mitigate the adverse effects of EM on the HMC architecture performance without requiring additional power and ground pins. Our benchmark-driven simulation-based analysis shows that compared to the clustered PDN layout, our proposed distributed PDN layout improves the EM-affected lifetime of the HMC architecture by up to 10 years. During this useful lifetime, the HMC architecture yields up to 1.51 times less energy-delay product (EDP).

中文翻译：

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基于 TSV 的供电网络支持 3D 堆叠 DRAM 中电迁移效应的表征和缓解

随着 3D 堆叠 DRAM 架构变得越来越普遍，找到表征和减轻可能阻碍其固有访问并行性和吞吐量的不利影响的方法变得很重要。此类逆境的一个例子是 3D 堆叠 DRAM 架构的供电网络 (PDN) 的硅通孔 (TSV) 中的电迁移 (EM) 效应。一些先前的工作已经解决了 EM 在 3D 集成电路的 TSV 中的影响。然而，之前的工作还没有解决 PDN TSV 中的 EM 对 3D 堆叠 DRAM 的性能和寿命的影响。在本文中，我们描述了 PDN TSV 中 EM 对混合存储立方体 (HMC) 架构的影响，该架构采用具有电源和接地 TSV 集群布局的传统 PDN 设计。然后，我们展示了一种具有电源和接地 TSV 分布式布局的新 PDN 设计，并表明它可以减轻 EM 对 HMC 架构性能的不利影响，而无需额外的电源和接地引脚。我们基于基准驱动的模拟分析表明，与集群 PDN 布局相比，我们提出的分布式 PDN 布局将 HMC 架构的受电磁影响的寿命提高了 10 年。在此使用寿命期间，HMC 架构产生的能量延迟积 (EDP) 最多可减少 1.51 倍。我们提出的分布式 PDN 布局将 HMC 架构受 EM 影响的寿命提高了 10 年。在此使用寿命期间，HMC 架构产生的能量延迟积 (EDP) 最多可减少 1.51 倍。我们提出的分布式 PDN 布局将 HMC 架构受 EM 影响的寿命提高了 10 年。在此使用寿命期间，HMC 架构产生的能量延迟积 (EDP) 最多可减少 1.51 倍。