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Analysis and Mitigation of Single-Event Gate Rupture in VDMOS With Termination Structure
IEEE Transactions on Nuclear Science ( IF 1.9 ) Pub Date : 2021-05-04 , DOI: 10.1109/tns.2021.3077244
Zhuojun Chen , Chenchen Zhang , Ming Wu , Teng Wang , Yun Zeng , Xin Wan , Hu Jin , Jun Xu , Minghua Tang

During heavy-ion experiments, the single-event gate rupture (SEGR) effects can still be observed in the vertical double-diffused power MOSFET (VDMOS) with radiation-hardened cells. Fault analysis demonstrates that the hot spots locate at the termination of the VDMOS. Then, several mitigation solutions for termination structure are discussed comprehensively by means of TCAD simulations. Finally, a combined hardness method with horizontally extending P+ region and adding floating N+ region is proposed. It is effective to reduce the electric field of gate oxide to below the calculated critical field, without additional masks and process steps.

中文翻译:


端接结构VDMOS中单粒子栅极击穿的分析与缓解



在重离子实验中,在具有抗辐射单元的垂直双扩散功率 MOSFET (VDMOS) 中仍然可以观察到单粒子栅极破裂 (SEGR) 效应。故障分析表明,热点位于VDMOS的端接处。然后通过TCAD模拟综合讨论了端接结构的几种缓解方案。最后,提出了水平延伸P+区域和添加浮动N+区域的组合硬度方法。无需额外的掩模和工艺步骤,即可有效地将栅极氧化物的电场降低至计算的临界场以下。
更新日期:2021-05-04
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