Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

中文翻译：

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一种有效的基于 CNTFET 的逻辑电路的可靠性估计方法

碳纳米管场效应晶体管 (CNTFET) 作为一种有前途的技术被广泛研究，被包括在后互补金属氧化物半导体集成电路中。尽管在延迟和功耗方面具有显着优势，但 CNTFET 的制造过程仍受到故障发生的困扰。因此，开发一种快速准确的方法来评估基于 CNTFET 的数字电路的可靠性是本研究的主要目标。在所提出的方法中，与发生在栅极晶体管中的故障相关的影响首先表示为概率传递矩阵。接下来，按拓扑顺序遍历目标电路的图，并计算电路门的可靠性。通过对 ISCAS 85 基准电路的各种模拟，验证了该方法的准确性（小于 3% 的可靠性估计误差）。所提出的方法在准确性和计算复杂度方面都优于以前的方法。