This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

中文翻译：

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MISTY1 块密码高速实现的设计空间探索

本文提出了 MISTY1 分组密码的 2 × 展开高速架构，用于无线应用，包括传感器网络和图像加密。利用双边沿触发 (DET) 和单边沿触发 (SET) 流水线对 8 轮 MISTY1 进行设计空间探索，以分析速度/面积的权衡。该设计主要基于 MISTY1 及其核心转换功能的查找表 (LUT) 的优化实现。LUT 是通过逻辑公式化 S9/S7 s-boxes 和 FI 以及 {FO + 32-bit XOR} 函数与流水线的精细放置来设计的。因此，在现场可编程门阵列 (FPGA)、Virtex-7、XC7VX690T 上获得并实现了高效和高速的 MISTY1 架构。高速/超高速 MISTY1 架构的吞吐量值为 25。2/43 Gbps 分别覆盖 1331/1509 个 CLB 切片的区域。建议的 MISTY1 架构优于所有以前的 MISTY1 实现，表明高速、小面积实现高效率值。所提出的架构比现有的 AES 和 Camellia 架构具有更高的效率值。这意味着对提议的高速 MISTY1 架构进行了优化。