Interleaving is a powerful technique that boosts the speed of an ADC. The power efficiency of such a technique is mainly affected by the overhead of the circuitry used to mitigate the impact of inter-channel mismatches on the ADC's performance. This paper reviews some of the most important methods of calibrating such mismatches and presents a frequency-domain analysis of timing skew in a time-interleaved (TI) ADC. A new calibration approach is also proposed that calibrates the timing and offset mismatches between the channels simultaneously. Behavioral modeling simulations of a 15-channel 10-b 2GS/s TI SAR ADC show an improvement of 35 dB in the SFDR after calibration. The impact of circuit nonidealities and noise is also assessed, and mitigation techniques are proposed.

中文翻译：

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时间交错 SAR ADC 的通道间失配校准技术


交错是一种强大的技术，可以提高 ADC 的速度。这种技术的功率效率主要受用于减轻通道间失配对 ADC 性能影响的电路开销的影响。本文回顾了校准此类失配的一些最重要的方法，并提出了时间交错 (TI) ADC 中时序偏差的频域分析。还提出了一种新的校准方法，可以同时校准通道之间的定时和偏移失配。 15 通道 10-b 2GS/s TI SAR ADC 的行为建模仿真显示，校准后 SFDR 提高了 35 dB。还评估了电路非理想性和噪声的影响，并提出了缓解技术。