Commercial electronic design automation (EDA) tools typically focus on optimizing the power, area, and speed of integrated circuits (ICs). They rarely consider hardware security requirements. As such, existing EDA tools often directly or indirectly introduce security vulnerabilities. These security vulnerabilities can later be exploited by attackers to leak information or compromise the hardware root-of-trust. In this paper, we show how traditional EDA tools optimize power, area and speed (PAS) metrics in cryptographic circuits at the cost of introducing vulnerabilities to side-channel analysis (SCA) attacks. To balance hardware security with traditional performance metrics, we propose an automatic tool, called CAD4EM-CLK, to secure ICs against power and electromagnetic (EM) SCA attacks. The tool optimizes clock networks for both traditional design requirements and security constraints. To achieve this goal, we first theoretically analyze and model the relationship between on-chip clock networks and side-channel security. The developed model will then guide the CAD4EM-CLK tool to adjust clock network structures to spread the leakage out temporally, also lower its amplitude proportion, so as to help reduce the leaked information. The proposed automatic tool is then validated on various cryptographic circuits. We use layout-level simulation to assess side-channel leakage and the experimental results prove the effectiveness of our proposed tool for power and EM side-channel protection.

中文翻译：

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用于电磁侧通道保护的自动片上时钟网络优化


商业电子设计自动化 (EDA) 工具通常专注于优化集成电路 (IC) 的功耗、面积和速度。他们很少考虑硬件安全要求。因此，现有的 EDA 工具经常直接或间接引入安全漏洞。这些安全漏洞稍后可能被攻击者利用来泄露信息或破坏硬件信任根。在本文中，我们展示了传统 EDA 工具如何优化加密电路中的功耗、面积和速度 (PAS) 指标，但代价是引入侧通道分析 (SCA) 攻击漏洞。为了平衡硬件安全性与传统性能指标，我们提出了一种名为 CAD4EM-CLK 的自动工具，以保护 IC 免受电源和电磁 (EM) SCA 攻击。该工具针对传统设计要求和安全约束优化时钟网络。为了实现这一目标，我们首先对片上时钟网络和旁路安全之间的关系进行理论分析和建模。然后，开发的模型将引导CAD4EM-CLK工具调整时钟网络结构，将泄漏时间分散，并降低其幅度比例，从而有助于减少泄漏信息。然后，所提出的自动工具在各种加密电路上进行验证。我们使用布局级仿真来评估侧通道泄漏，实验结果证明了我们提出的电源和电磁侧通道保护工具的有效性。