Architectural studies of the cache and memory hierarchy need a fast simulation model for the processor core that accurately conveys the impact of memory subsystem changes on application performance. We propose the RIO model (ROB-centric In-order model for Out-of-order cores), a single-pass core performance model based on finding the earliest possible future issue time for out-of-order execution. RIO can natively model second-order effects of overlapping and interacting miss events, significantly improving accuracy over interval simulation. Yet it is no more complex to implement and run, providing a compelling speedup over more detailed models. We implement RIO in Sniper and evaluate it on 2000+ application traces, and find it has an average absolute prediction error of 10.3 percent over Sniper's most detailed model, while simulating 2.8× faster on average (up to 5× on memory-bound workloads).

中文翻译：

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RIO：以 ROB 为中心的无序处理器的有序建模


缓存和内存层次结构的架构研究需要处理器核心的快速仿真模型，以准确地传达内存子系统变化对应用程序性能的影响。我们提出了 RIO 模型（用于乱序核心的以 ROB 为中心的有序模型），这是一种基于寻找乱序执行的最早可能的未来发布时间的单通道核心性能模型。 RIO 可以对重叠和相互作用的缺失事件的二阶效应进行原生建模，从而显着提高间隔模拟的准确性。然而，它的实现和运行并不复杂，与更详细的模型相比，提供了引人注目的加速。我们在 Sniper 中实现 RIO 并在 2000 多个应用程序跟踪上对其进行评估，发现与 Sniper 最详细的模型相比，它的平均绝对预测误差为 10.3%，同时模拟速度平均提高 2.8 倍（在内存受限的工作负载上高达 5 倍） 。