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Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals
Circuits, Systems, and Signal Processing ( IF 1.8 ) Pub Date : 2021-03-25 , DOI: 10.1007/s00034-020-01620-6
Andrei B. La Rosa , Pedro T. L. Pereira , Patrícia Ücker , Guilherme Paim , Eduardo A. C. da Costa , Sergio Bampi , Sérgio Almeida

Electroencephalogram (EEG) is a biomedical technique for capturing the human brain’s electrical information to process its activities and actions. EEG is one of the main methods commonly used in neuroscience, from clinical analysis to the design of brain–computer interfaces. The first one of the many challenges in an EEG system design regards the ultra-low amplitude of signals (i.e., of the order of \(20~\upmu \hbox {V}\)) and their susceptibility to several kinds of interferences. Electromagnetic interference (EMI) omnidirectionally irradiated by the power line supplies disturbs the EEG instrumentation system with a noise power mostly concentrated from 50 to \(60\,\hbox {Hz}\). Our paper investigates the energy efficiency of adaptive filtering (AF) techniques based on the least mean square (LMS), normalized LMS, and set-membership (SM) families for meeting the protection against EMI in EEG systems. The results demonstrate that the LMS algorithm presents an unstable behavior with unsatisfactory results against the normalized LMS filters when subject to noisy scenarios. Therefore, we herein explore dedicated VLSI hardware architectures for the following filters: (a) normalized LMS (NLMS), (b) SM-NLMS, (c) partial update NLMS (PU-NLMS), and (d) SM bi-normalized LMS (SM-BNLMS). PU-NLMS architecture offers the best trade-off between the capability of eliminating the EMI versus its power dissipation, circuit area, and maximum clock frequency. PU-NLMS provides an artifact reduction level of up to \(8.8\,\hbox {dB}\), with low energy consumption of 0.62 nJ/operation and just \(1.41\%\) larger circuit area than the NLMS architecture.



中文翻译:

探索基于 NLMS 的自适应滤波器硬件架构,以消除 EEG 信号中的电力线干扰

脑电图 (EEG) 是一种生物医学技术,用于捕获人脑的电信息以处理其活动和动作。脑电图是神经科学中常用的主要方法之一,从临床分析到脑机接口的设计。EEG 系统设计中的众多挑战中的第一个与信号的超低幅度(即\(20~\upmu \hbox {V}\) 的数量级)及其对多种干扰的敏感性有关。电源线全向辐射的电磁干扰 (EMI) 干扰 EEG 仪器系统,噪声功率主要集中在 50 到\(60\,\hbox {Hz}\). 我们的论文研究了基于最小均方 (LMS)、归一化 LMS 和集合成员 (SM) 系列的自适应滤波 (AF) 技术的能效,以满足 EEG 系统中的 EMI 保护。结果表明,当遇到噪声场景时,LMS 算法表现出不稳定的行为,对归一化 LMS 滤波器的结果不令人满意。因此,我们在此探索用于以下滤波器的专用 VLSI 硬件架构:(a) 归一化 LMS (NLMS),(b) SM-NLMS,(c) 部分更新 NLMS (PU-NLMS),以及 (d) SM 双归一化LMS (SM-BNLMS)。PU-NLMS 架构在消除 EMI 的能力与其功耗、电路面积和最大时钟频率之间提供了最佳权衡。PU-NLMS 提供了高达\(8.8\,\hbox {dB}\),具有 0.62 nJ/操作的低能耗和比 NLMS 架构大\(1.41\%\) 的电路面积。

更新日期:2021-03-25
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