A novel physics-based simulation model of electromigration (EM) and stress-migration (SM) induced degradation of electrical characteristics of on-chip interconnects is developed based on the coupled evolution of stress and voiding resolved by means of finite element simulations (FEM). The void evolution tracked with the phase field methodology, is linked with the evolution of EM/SM induced stress, which are generated in the metal segments by the interaction of the inelastic deformations due to divergences of atomic fluxes with the rigid confinement. Accounted atomic exchange between the metal and void surface removes a limitation on the void volume conservation. Developed simulation methodology allows to predict effects of the metal segment architecture and geometry, metal morphology and texture, as well as atomic diffusivities along the variety of migration venues on voiding-induced degradation of interconnect electrical conductance. Results of performed simulation indicate that the pre-existed stress induced voids (SIV) can evolve under the action of applied electric current and affect interconnect reliability. The developed physics-based simulation methodology can help to address reliability concerns by optimizing the properties of interconnect materials and modifying the physical design of the interconnect layouts in order to achieve EM resistant on-chip interconnects.

基于通过有限元模拟 (FEM) 解决的应力和空洞的耦合演化，开发了一种基于物理的新型电迁移 (EM) 和应力迁移 (SM) 诱导的片上互连电气特性退化模型. 用相场方法跟踪的空隙演变与 EM/SM 诱导应力的演变有关，这些应力是由于原子通量发散与刚性限制导致的非弹性变形相互作用而在金属段中产生的。金属和空隙表面之间的原子交换消除了对空隙体积守恒的限制。开发的模拟方法允许预测金属段结构和几何形状、金属形态和纹理的影响，以及沿各种迁移场所的原子扩散率对互连电导的空洞引起的退化。执行模拟的结果表明，预先存在的应力诱导空隙 (SIV) 会在外加电流的作用下演变并影响互连可靠性。开发的基于物理的仿真方法可以通过优化互连材料的特性和修改互连布局的物理设计来帮助解决可靠性问题，以实现抗电磁干扰的片上互连。