The effects of soft error in combinational logics are challenged by decreasing the feature size of transistors in nanoscale technologies. Moreover, the single event transients (SETs) caused by particle strikes, manifesting multiple event transients (METs), are expectable, as well. Coping with this problem is the end of CLEAR using a cross-layer method as an effective way to mitigate the rate of double event transients (DETs) in combinational logic. First, an algorithm is proposed based on local displacements and linear programming (LP) optimization problem, which locates the cells in the best way from the DETs point of view. Next, two hardening methods are proposed based on resizing and fault masking. Finally, one of these two methods is applied to the aforesaid algorithm results, modified layout, considering the given design parameters. Experimental studies reveal a reduction of 42.9% on average in DETs rate, which can be improved up to 51.1% and 68.9% by applying two aforementioned hardening methods with some negligible overhead.

通过减小纳米级技术中晶体管的特征尺寸，对组合逻辑中软错误的影响提出了挑战。此外，由粒子撞击引起的单事件瞬态 (SET) 表现出多事件瞬态 (MET)，也是可以预期的。解决这个问题是 CLEAR 的终结，它使用跨层方法作为减轻组合逻辑中双事件瞬态 (DET) 率的有效方法。首先，提出了一种基于局部位移和线性规划 (LP) 优化问题的算法，该算法从 DET 的角度以最佳方式定位细胞。接下来，提出了两种基于调整大小和故障屏蔽的硬化方法。最后，将这两种方法中的一种应用于上述算法结果，修改布局，考虑给定的设计参数。