Lateral parasitic PNP transistor inside P+/N-well diode is explored and investigated for the electrostatic discharge (ESD) protections in I/O interface integrated circuits (ICs). An analysis for the breakdown behavior of the lateral parasitic PNP transistor with base floating is presented for the first time. Simulations on the lateral parasitic PNP transistor have been performed to understand the effects of geometry parameters on current gain β, triggering voltage V_t1 and on-resistance R_ON. The test structures were fabricated using the UMC 65 nm low-k logic/mixed-mode CMOS process and characterized with the transmission line pulse (TLP) system. The TLP characterization results demonstrate that the triggering voltage V_t1 is strongly influenced by the base region (i.e., base width), and on-resistance R_ON is mainly affected by the collector region (i.e., collector width) for the finger-type parasitic PNP. Meanwhile, the scalability of thermal failure current I_t2 has been studied in terms of the periphery of the lateral parasitic PNP and the whole device width.

探索和研究 P+/N 阱二极管内的横向寄生 PNP 晶体管，用于 I/O 接口集成电路 (IC) 中的静电放电 (ESD) 保护。首次对具有基极浮动的横向寄生 PNP 晶体管的击穿行为进行了分析。对横向寄生 PNP 晶体管进行了仿真，以了解几何参数对电流增益β、触发电压V _t1和导通电阻R _{ON 的影响}。测试结构使用 UMC 65 nm 低 k 逻辑/混合模式 CMOS 工艺制造，并使用传输线脉冲 (TLP) 系统进行表征。TLP 表征结果表明，触发电压V_T1是强烈基极区域（即，基极宽度）的影响，并且导通电阻- [R _ON主要受对手指型寄生PNP集电极区域（即，集电体的宽度）。同时，从横向寄生 PNP 的外围和整个器件宽度方面研究了热故障电流I _t2的可扩展性。